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An Overview of Cache Memory in Memory Management
Automation, Control and Intelligent Systems
Volume 8, Issue 3, June 2020, Pages: 24-28
Received: Jul. 14, 2020; Accepted: Aug. 7, 2020; Published: Oct. 30, 2020
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Ademodi Oluwatosin Abayomi, Computer Engineering Department, School of Engineering, Lagos State Polytechnics, Ikorodu, Lagos, Nigeria
Ajayi Abayomi Olukayode, Computer Engineering Department, School of Engineering, Lagos State Polytechnics, Ikorodu, Lagos, Nigeria
Green Oluwole Olakunle, Computer Engineering Department, School of Engineering, Lagos State Polytechnics, Ikorodu, Lagos, Nigeria
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Cache memory are used in small, medium and high speed Central Processing Unit (CPU) to hold provisionally those content of the main memory which are currently in use. Preferably, Caches ought to have low miss rates, short access times, and power efficient at the same time. The design objectives are frequently gainsaying in practice. Nowadays, security concern about caches information outflow is based on the proficient attack of the information in the memory and the design for security in the cache memory are even more controlled and typically leads to significant cache performance. Fault tolerance is an additional advantage of the cache architecture which can be guaranteed in the memory to overcome the processor speed gap in the memory, the routine gap between processors and main memory continues to broaden, increasingly aggressive implementations of cache memories are needed to bridge the gap. In this paper, the objective is to make cache memory unsurprising as seen by the processor, so it can be used in hard real time system to achieve this we consider some of the issues that are involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the increasingly stringent design targets.
Cache Memory, Central Processing Unit, Main Memory, Processor
To cite this article
Ademodi Oluwatosin Abayomi, Ajayi Abayomi Olukayode, Green Oluwole Olakunle, An Overview of Cache Memory in Memory Management, Automation, Control and Intelligent Systems. Vol. 8, No. 3, 2020, pp. 24-28. doi: 10.11648/j.acis.20200803.11
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This article is an open access article distributed under the Creative Commons Attribution License ( which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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