Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.
| Published in | Science Journal of Circuits, Systems and Signal Processing (Volume 8, Issue 2) |
| DOI | 10.11648/j.cssp.20190802.16 |
| Page(s) | 76-81 |
| Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
| Copyright |
Copyright © The Author(s), 2024. Published by Science Publishing Group |
Carry Look-ahead Adder, 4-Bit Adder, Xor Gate, And Gate, Carry-Propagate
| [1] | N. H. Weste, D. M. Harris, CMOS VLSI Design: A Circuit and Systems Perspective, Addison and Wesley, 2010. |
| [2] | M. Hasan, M. H. Anik and S. Islam, “Microcontroller Based Smart Home System with Enhanced Appliance Switching Capacity,” 2018 Fifth HCT Information Technology Trends (ITT), Dubai, United Arab Emirates, 2018, pp. 364-367. |
| [3] | M. H. Zaman, E. T. Carlen and C. H. Mastrangelo, “Automatic generation of thin film process flows. II. Recipe generation, flow evaluation, and system framework,” in IEEE Transactions on Semiconductor Manufacturing, vol. 12, no. 1, pp. 129-138, Feb. 1999. |
| [4] | M. Hasan, P. Biswas, M. T. I. Bilash and M. A. Z. Dipto, “Smart Home Systems: Overview and Comparative Analysis,” 2018 Fourth International Conference on Research in Computational Intelligence and Communication Networks (ICRCICN), Kolkata, India, 2018, pp. 264-268. |
| [5] | M. H. Zaman, E. T. Carlen and C. H. Mastrangelo, “Automatic generation of thin film process flows. I. Basic algorithms,” in IEEE Transactions on Semiconductor Manufacturing, vol. 12, no. 1, pp. 116-128, Feb. 1999. |
| [6] | M. Hasan, M. H. Anik, S. Chowdhury, S. A. Chowdhury, M. T. I. Bilash, S. Islam, “Low-cost Appliance Switching Circuit for Discarding Technical Issues of Microcontroller Controlled Smart Home,” International Journal of Sensors and Sensor Networks. vol. 7, no. 2, pp. 16-22, 2019. |
| [7] | R. Hossain, M. Ahmed, H. U. Zaman, “A Cost Effective Security Technology Integrated with RFID Based Automated Toll Collection System,” Advances in Science, Technology and Engineering Systems Journal Vol. 2, no. 3, pp. 1777-1783, 2017. |
| [8] | S. A. Karim and H. U. Zaman, “Simulation and visualization of carrier trajectories in distributed MIGFET devices a simulation of newtonian particles at small dimensions,” 2016 19th International Conference on Computer and Information Technology (ICCIT), Dhaka, 2016, pp. 139-144. |
| [9] | S. A. Karim and H. U. Zaman, “ualitative analysis of an equivalent full adder circuit using MIGFET: An alternative approach to full adder circuit via direct truth table implementation,” 2016 International Conference on Microelectronics, Computing and Communications (MicroCom), Durgapur, 2016, pp. 1-6. |
| [10] | M. Hasan, A. Z. Dipto, M. S. Islam, A. Sorwar, S. Alam, “A Smart Semi-Automated Multifarious Surveillance Bot for Outdoor Security Using Thermal Image Processing,” Advances in Networks. vol. 7, no. 2, pp. 21-28, 2019. |
| [11] | J. Warnock et al., “Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module,” in IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 9-18, Jan. 2014. |
| [12] | H. Naseri and S. Timarchi, “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1481-1493, Aug. 2018. |
| [13] | S. Perri, M. Lanuzza, P. Corsonello, “Design of high-speed low-power parallel-prefix adder trees in nanometer technologies,” International Journal of Circuit Theory and Applications, vol. 42, pp. 731-743, 2014. |
| [14] | M. Hasanuzzaman and C. H. Mastrangelo, “Process compilation of thin film microdevices,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 7, pp. 745-764, July 1996. |
| [15] | A. Gard, G Joshi, “Gate diffusion input based 4-bit vedic multiplier design,” IET Circuits, Devices and Systems, vol. 12, no. 6, pp. 764-770, 2018. |
| [16] | H. Xue, R. Patel, N. V. V. K. Boppana and S. Ren, “Low-power-delay-product radix-4 8*8 Booth multiplier in CMOS,” in Electronics Letters, vol. 54, no. 6, pp. 344-346, 22 3 2018. |
| [17] | I. Hussain, C. K. Pandey and S. Chaudhury, “Design and Analysis of High Performance Multiplier Circuit,” 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 245-247. |
| [18] | M. Hasan, M. J. Hossein, U. K. Saha and M. S. Tarif, “Overview and Comparative Performance Analysis of Various Full Adder Cells in 90 nm Technology,” 2018 4th International Conference on Computing Communication and Automation (ICCCA), Greater Noida, India, 2018, pp. 1-6. |
| [19] | M. Hasan, U. K. Saha, A. Sorwar, M. A. Z. Dipto, M. S. Hossain, H. U. Zaman, “A Novel Hybrid Full Adder Based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic,” 2019 10th International Conference on Computing, Communication and Networking Technologies, Kanpur, 2019. |
| [20] | G. Sasi, G. Athisha, S. Surya prakash, “Performance Comparison for Ripple Carry Adder Using Various Logic Design,” International Journal of Innovative Technology and Exploring Engineering (IJITEE), vol. 8, pp. 372-377, 2019. |
| [21] | K. Papachatzopoulos and V. Paliouras, “Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2546-2559, July 2019. |
| [22] | M. Hasan, U. K. Saha, M. S. Hossain, P. Biswas, M. J. Hossein and M. A. Z. Dipto, “Low Power Design of a Two Bit Mangitude Comparator for High Speed Operation,” 2019 International Conference on Computer Communication and Informatics (ICCCI), Coimbatore, Tamil Nadu, India, 2019, pp. 1-4. |
| [23] | S. Ghosh and K. Roy, “Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1504-1507, Aug. 2011. |
| [24] | C. Efstathiou, Z. Owda and Y. Tsiatouhas, “New High-Speed Multioutput Carry Look-Ahead Adders,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 10, pp. 667-671, Oct. 2013. |
| [25] | O. Akbari, M. Kamal, A. Afzali-Kusha and M. Pedram, “RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 8, pp. 1089-1093, Aug. 2018. |
| [26] | M. R. Nandini, P. Mor and J. M. Keller, “A Comparative Study of Static and Dynamic CMOS Logic,” International Journal of Current Engineering and Technology, vol. 6, no. 3, pp. 1019-1021, 2016. |
| [27] | M. Hasan, M. Hasan, M. J. Hossein, M. Hossain, H. U. Zaman and S. Islam, “Design of a Scalable Low-Power 1-bit Hybrid Full Adder for Fast Computation,” in IEEE Transactions on Circuits and Systems II: Express Briefs, 2019. |
| [28] | V. Forutan, M. Taheri, A. Mazreah, “Design of two low power full adder cells using GDI structure and hybrid CMOS logic style”, Integration (Amst), vol. 47, no. 1, pp. 48-61, 2014. |
| [29] | A. M. Shams, D. K. Darwish, M. A. Bayoumi, “Performance analysis of low power 1-bit CMOS full adder cells,” IEEE Transactions of Very Large Scale Integration (VLSI) Systems, vol. 10, no. 1, pp. 20-29, 2002. |
| [30] | P. Suveetha Dhanaselvam, K. Hamsa Nandhini, M. Rajammal, S. Satheeswari, “Design and Implementation of 16-Bit Carry Look Ahead Adder Using Cadence Tool,” International Journal of Engineering Research & Technology (IJERT), vol. 5, no. 9, pp. 1-6, 2017. |
| [31] | J. Miao and S. Li, “A novel implementation of 4-bit carry look-ahead adder,” 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, 2017, pp. 1-2. |
| [32] | S. Ghafari, M. Mousazadeh, A. Khoei and A. Dadashi, “A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method,” 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 157-162. |
| [33] | M. Hasan, P. Biswas, M. S. Alam, H. U. Zaman, M. Hossain and S. Islam, “High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder,” 2019 10th International Conference on Computing, Communication and Networking Technologies, Kanpur, 2019. |
| [34] | N. R. Swart, S. F. Bart, M. H. Zaman, M. Mariappan, J. R. Gilbert and D. Murphy, “AutoMM: automatic generation of dynamic macromodels for MEMS devices," Proceedings MEMS 98. IEEE. Eleventh Annual International Workshop on Micro Electro Mechanical Systems. An Investigation of Micro Structures, Sensors, Actuators, Machines and Systems (Cat. No.98CH36176, Heidelberg, Germany, 1998, pp. 178-183. |
| [35] | R. Hossain, M. Ahmed, H. U. Zaman and M. A. Nazim, "A comparative study of various simulation software for design and analysis of operational amplifier based integrator circuits," 2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON), Bangkok, 2017, pp. 278-282. |
| [36] | M. F. Karin, K. S. Noor and H. U. Zaman, “Hardware based design and implementation of a bottle recycling machine using FPGA,” 2016 IEEE Conference on Systems, Process and Control (ICSPC), Bandar Hilir, 2016, pp. 43-46. |
APA Style
Mehedi Hasan, Moumita Sadia Islam, Muhtasim Rafid Ahmed. (2019). Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms. Science Journal of Circuits, Systems and Signal Processing, 8(2), 76-81. https://doi.org/10.11648/j.cssp.20190802.16
ACS Style
Mehedi Hasan; Moumita Sadia Islam; Muhtasim Rafid Ahmed. Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms. Sci. J. Circuits Syst. Signal Process. 2019, 8(2), 76-81. doi: 10.11648/j.cssp.20190802.16
AMA Style
Mehedi Hasan, Moumita Sadia Islam, Muhtasim Rafid Ahmed. Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms. Sci J Circuits Syst Signal Process. 2019;8(2):76-81. doi: 10.11648/j.cssp.20190802.16
Share This Article
Twitter
Linked In
Facebook
Copy
Download@article{10.11648/j.cssp.20190802.16,
author = {Mehedi Hasan and Moumita Sadia Islam and Muhtasim Rafid Ahmed},
title = {Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms},
journal = {Science Journal of Circuits, Systems and Signal Processing},
volume = {8},
number = {2},
pages = {76-81},
doi = {10.11648/j.cssp.20190802.16},
url = {https://doi.org/10.11648/j.cssp.20190802.16},
eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20190802.16},
abstract = {Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.},
year = {2019}
}
TY - JOUR T1 - Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms AU - Mehedi Hasan AU - Moumita Sadia Islam AU - Muhtasim Rafid Ahmed Y1 - 2019/12/27 PY - 2019 N1 - https://doi.org/10.11648/j.cssp.20190802.16 DO - 10.11648/j.cssp.20190802.16 T2 - Science Journal of Circuits, Systems and Signal Processing JF - Science Journal of Circuits, Systems and Signal Processing JO - Science Journal of Circuits, Systems and Signal Processing SP - 76 EP - 81 PB - Science Publishing Group SN - 2326-9073 UR - https://doi.org/10.11648/j.cssp.20190802.16 AB - Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements. VL - 8 IS - 2 ER -
Information
Email: