Delay Based Auto-Calibrated PVT Monitor System and Method

Alexandro Giron; Esteban Martinez; Victor Avendaño

doi:doi:10.11648/j.cssp.20200902.13

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Delay Based Auto-Calibrated PVT Monitor System and Method

Alexandro Giron, Esteban Martinez, Victor Avendaño

Published in Science Journal of Circuits, Systems and Signal Processing (Volume 9, Issue 2)

Received: 24 March 2020 Accepted: 15 April 2020 Published: 3 September 2020

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Abstract

In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP’s (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.

Published in	Science Journal of Circuits, Systems and Signal Processing (Volume 9, Issue 2)
DOI	10.11648/j.cssp.20200902.13
Page(s)	49-58
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2024. Published by Science Publishing Group

Keywords

Adaptive, Buffer Chain, Calibration, Delay Line, Flip-flop, Monitor, PVT, Setup Time

References

[1]	B. Nguyen, N. Tang, W. Hong, Z. Zhou, and D. Heo, “Clock-voltage co-regulator with adaptive power budget tracking for robust near-threshold-voltage sequential logic circuits,” in IEEE Transactions on Circuits and Systems, vol. 67, no. 2, pp. 622-633, Feb. 2020.
[2]	D. Rossi, et al., “A self-aware architecture for PVT compensation and power nap in near threshold processors,” in IEEE Design and Test, vol. 34, issue 6, pp. 46-53, Sept. 2017.
[3]	W. Shan, L. Shu, and J. Yang, “In-situ timing monitor-based adaptive voltage scaling system for wide-voltage-range applications,” in IEEE Access, vol. 5, pp. 15831-15838, Feb. 2017.
[4]	K. Shakeri and J. Meindl, “Temperature variable supply voltage for power reduction,” in IEEE Computer Society Annual Symp. on VLSI, pp. 64-67, Pittsburgh, United States, Apr. 2002.
[5]	C. V. Martins, J. Semiao, J. C. Vazquez, V. Champac, M. Santos, I. C. Texteira, and J. P. Texteira, “Adaptive error-prediction flip-flop for performance failure prediction with Aging Sensors” in 29th IEEE VLSI Test Symp., pp. 203-208, CA. USA, May. 2011.
[6]	D. Wolpert and P. Ampadu, “A low-power safety mode for variation tolerant systems-on-chip,” in IEEE Int. Symp. on Defect and Fault Tolerance of VLSI Systems, pp. 33-41, Boston, MA., Oct. 2008.
[7]	M. Nakai, et al., “Dynamic voltage and frequency management for a low-power embedded microprocessor,” in IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 28-35, Jan. 2005.
[8]	M. Hashimoto, “Run-time adaptive performance compensation using on-chip sensors,” in 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Yokohama, Japan, Jan. 2011.
[9]	M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y. Hagihara, “Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes,” in IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 805-814, United States, Apr. 2006.
[10]	M. Hashimoto, and H. Fuketa, “Adaptive performance compensation with on-chip variation monitoring,” in IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS), Seoul, South Korea, Sept. 2011.
[11]	T. Pavan, N. Jagannadha, and B. Shekar, “Implementation of delay and power monitoring schemes to reduce the power consumption,” in IEEE Proceedings of Int. Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), pp. 459-464, India, Jul. 2011.
[12]	T. Matsumoto, “High-resolution on-chip propagation delay detector for measuring within-chip variations,” in IEEE Int. Conference on Integrated Circuit and Technology, pp. 217-220, Austin, TX. United States, May 2005.
[13]	S. W. Chen, M. H. Chang, W. C. Hsieh, and W. Hwang, “Fully on-chip temperature, process, and voltage sensors,” in IEEE Int. Symp. on Circuit Systems (ISCAS), pp. 897-900, Paris, France, May 2010.
[14]	M. J. Chang, et al., “Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection,” in IEEE Int. Symp. on Circuits and Systems (ISCAS), pp 133-136, Beijing, China, Apr. 2013.
[15]	X. Wang, M. Tehranipoor, S. George, D. Tran, and L. Winemberg, “Design and analysis of a delay sensor applicable to process/environmental variations and aging measurements,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. vol. 20, no. 8, pp 1405-1418, Aug. 2012.
[16]	S. Gosh, S. Bhunia, A. Raychowdhury, and K. Roy, “Delay fault localization in test-per-scan BIST using built-in delay sensor” in 12th IEEE Int. On-Line Testing Symposium (IOLTS'06), Italy, Jul. 2006.
[17]	A. Bal, J. N. Tiwari, J. N. Triphati, and R. Achar “A novel programmable delay line for VLSI systems,” in IEEE 23rd Workshop on Signal and Power Integrity, Chambery, France. Jun. 2019.
[18]	J. I. Morales, F. Chierche, P. S. Mandolesi, and E. E. Paolini, “Design and evaluation of an all-digital programmable delay line in 130-nm CMOS,” in XVIII Workshop on Information Processing and Control, Bahia Blanca, Argentina. Sept. 2019.
[19]	S. Xie and W. T. Ng, “A 65nm CMOS low power delay line based temperature sensor,” in IEEE Int. Conference of Electron Devices and Solid-State Circuits, Tianjin, China. Nov. 2011.
[20]	A. Girón-Allende, V. Avendaño, and E. Martínez-Guerrero, "A design methodology using flip-flops controlled by PVT variation detection," IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2015), pp. 1-4. Montevideo, Uruguay, Feb. 2015.

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APA Style

Alexandro Giron, Esteban Martinez, Victor Avendaño. (2020). Delay Based Auto-Calibrated PVT Monitor System and Method. Science Journal of Circuits, Systems and Signal Processing, 9(2), 49-58. https://doi.org/10.11648/j.cssp.20200902.13

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ACS Style

Alexandro Giron; Esteban Martinez; Victor Avendaño. Delay Based Auto-Calibrated PVT Monitor System and Method. Sci. J. Circuits Syst. Signal Process. 2020, 9(2), 49-58. doi: 10.11648/j.cssp.20200902.13

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AMA Style

Alexandro Giron, Esteban Martinez, Victor Avendaño. Delay Based Auto-Calibrated PVT Monitor System and Method. Sci J Circuits Syst Signal Process. 2020;9(2):49-58. doi: 10.11648/j.cssp.20200902.13

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@article{10.11648/j.cssp.20200902.13,
  author = {Alexandro Giron and Esteban Martinez and Victor Avendaño},
  title = {Delay Based Auto-Calibrated PVT Monitor System and Method},
  journal = {Science Journal of Circuits, Systems and Signal Processing},
  volume = {9},
  number = {2},
  pages = {49-58},
  doi = {10.11648/j.cssp.20200902.13},
  url = {https://doi.org/10.11648/j.cssp.20200902.13},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20200902.13},
  abstract = {In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP’s (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.},
 year = {2020}
}

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TY  - JOUR
T1  - Delay Based Auto-Calibrated PVT Monitor System and Method
AU  - Alexandro Giron
AU  - Esteban Martinez
AU  - Victor Avendaño
Y1  - 2020/09/03
PY  - 2020
N1  - https://doi.org/10.11648/j.cssp.20200902.13
DO  - 10.11648/j.cssp.20200902.13
T2  - Science Journal of Circuits, Systems and Signal Processing
JF  - Science Journal of Circuits, Systems and Signal Processing
JO  - Science Journal of Circuits, Systems and Signal Processing
SP  - 49
EP  - 58
PB  - Science Publishing Group
SN  - 2326-9073
UR  - https://doi.org/10.11648/j.cssp.20200902.13
AB  - In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP’s (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.
VL  - 9
IS  - 2
ER  -

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Author Information

Alexandro Giron

Electronics, Systems, and Informatics Department, Western Institute of Technology and Higher Education, Guadalajara, Mexico
Esteban Martinez

Electronics, Systems, and Informatics Department, Western Institute of Technology and Higher Education, Guadalajara, Mexico
Victor Avendaño

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Plain Text BibTeX RIS

APA Style

Alexandro Giron, Esteban Martinez, Victor Avendaño. (2020). Delay Based Auto-Calibrated PVT Monitor System and Method. Science Journal of Circuits, Systems and Signal Processing, 9(2), 49-58. https://doi.org/10.11648/j.cssp.20200902.13

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ACS Style

Alexandro Giron; Esteban Martinez; Victor Avendaño. Delay Based Auto-Calibrated PVT Monitor System and Method. Sci. J. Circuits Syst. Signal Process. 2020, 9(2), 49-58. doi: 10.11648/j.cssp.20200902.13

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AMA Style

Alexandro Giron, Esteban Martinez, Victor Avendaño. Delay Based Auto-Calibrated PVT Monitor System and Method. Sci J Circuits Syst Signal Process. 2020;9(2):49-58. doi: 10.11648/j.cssp.20200902.13

Copy | Download

@article{10.11648/j.cssp.20200902.13,
  author = {Alexandro Giron and Esteban Martinez and Victor Avendaño},
  title = {Delay Based Auto-Calibrated PVT Monitor System and Method},
  journal = {Science Journal of Circuits, Systems and Signal Processing},
  volume = {9},
  number = {2},
  pages = {49-58},
  doi = {10.11648/j.cssp.20200902.13},
  url = {https://doi.org/10.11648/j.cssp.20200902.13},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20200902.13},
  abstract = {In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP’s (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.},
 year = {2020}
}

Copy | Download

TY  - JOUR
T1  - Delay Based Auto-Calibrated PVT Monitor System and Method
AU  - Alexandro Giron
AU  - Esteban Martinez
AU  - Victor Avendaño
Y1  - 2020/09/03
PY  - 2020
N1  - https://doi.org/10.11648/j.cssp.20200902.13
DO  - 10.11648/j.cssp.20200902.13
T2  - Science Journal of Circuits, Systems and Signal Processing
JF  - Science Journal of Circuits, Systems and Signal Processing
JO  - Science Journal of Circuits, Systems and Signal Processing
SP  - 49
EP  - 58
PB  - Science Publishing Group
SN  - 2326-9073
UR  - https://doi.org/10.11648/j.cssp.20200902.13
AB  - In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP’s (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.
VL  - 9
IS  - 2
ER  -

Copy | Download