Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz

M. Dashtbayazi; M. Sabaghi; S. Marjani

doi:doi:10.11648/j.jeee.20150304.15

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Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz

M. Dashtbayazi, M. Sabaghi, S. Marjani

Published in Journal of Electrical and Electronic Engineering (Volume 3, Issue 4)

Received: 15 March 2015 Accepted: 27 April 2015 Published: 13 August 2015

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Abstract

A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply

Published in	Journal of Electrical and Electronic Engineering (Volume 3, Issue 4)
DOI	10.11648/j.jeee.20150304.15
Page(s)	93-96
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2024. Published by Science Publishing Group

Keywords

Comparator, Negative Resistance, Optical Communication Systems, Transconductance Boosting, Dual-Rail Differential Input

References

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APA Style

M. Dashtbayazi, M. Sabaghi, S. Marjani. (2015). Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. Journal of Electrical and Electronic Engineering, 3(4), 93-96. https://doi.org/10.11648/j.jeee.20150304.15

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ACS Style

M. Dashtbayazi; M. Sabaghi; S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. J. Electr. Electron. Eng. 2015, 3(4), 93-96. doi: 10.11648/j.jeee.20150304.15

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AMA Style

M. Dashtbayazi, M. Sabaghi, S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. J Electr Electron Eng. 2015;3(4):93-96. doi: 10.11648/j.jeee.20150304.15

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@article{10.11648/j.jeee.20150304.15,
  author = {M. Dashtbayazi and M. Sabaghi and S. Marjani},
  title = {Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz},
  journal = {Journal of Electrical and Electronic Engineering},
  volume = {3},
  number = {4},
  pages = {93-96},
  doi = {10.11648/j.jeee.20150304.15},
  url = {https://doi.org/10.11648/j.jeee.20150304.15},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20150304.15},
  abstract = {A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply},
 year = {2015}
}

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TY  - JOUR
T1  - Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz
AU  - M. Dashtbayazi
AU  - M. Sabaghi
AU  - S. Marjani
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DO  - 10.11648/j.jeee.20150304.15
T2  - Journal of Electrical and Electronic Engineering
JF  - Journal of Electrical and Electronic Engineering
JO  - Journal of Electrical and Electronic Engineering
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EP  - 96
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AB  - A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply
VL  - 3
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ER  -

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Author Information

M. Dashtbayazi

Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
M. Sabaghi

Laser and Optics Research School, Nuclear Science and Technology Research Institute (NSTRI), Tehran, Iran
S. Marjani

Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran

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APA Style

M. Dashtbayazi, M. Sabaghi, S. Marjani. (2015). Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. Journal of Electrical and Electronic Engineering, 3(4), 93-96. https://doi.org/10.11648/j.jeee.20150304.15

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ACS Style

M. Dashtbayazi; M. Sabaghi; S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. J. Electr. Electron. Eng. 2015, 3(4), 93-96. doi: 10.11648/j.jeee.20150304.15

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AMA Style

M. Dashtbayazi, M. Sabaghi, S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz. J Electr Electron Eng. 2015;3(4):93-96. doi: 10.11648/j.jeee.20150304.15

Copy | Download

@article{10.11648/j.jeee.20150304.15,
  author = {M. Dashtbayazi and M. Sabaghi and S. Marjani},
  title = {Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz},
  journal = {Journal of Electrical and Electronic Engineering},
  volume = {3},
  number = {4},
  pages = {93-96},
  doi = {10.11648/j.jeee.20150304.15},
  url = {https://doi.org/10.11648/j.jeee.20150304.15},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20150304.15},
  abstract = {A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply},
 year = {2015}
}

Copy | Download

TY  - JOUR
T1  - Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz
AU  - M. Dashtbayazi
AU  - M. Sabaghi
AU  - S. Marjani
Y1  - 2015/08/13
PY  - 2015
N1  - https://doi.org/10.11648/j.jeee.20150304.15
DO  - 10.11648/j.jeee.20150304.15
T2  - Journal of Electrical and Electronic Engineering
JF  - Journal of Electrical and Electronic Engineering
JO  - Journal of Electrical and Electronic Engineering
SP  - 93
EP  - 96
PB  - Science Publishing Group
SN  - 2329-1605
UR  - https://doi.org/10.11648/j.jeee.20150304.15
AB  - A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply
VL  - 3
IS  - 4
ER  -

Copy | Download