Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz
Journal of Electrical and Electronic Engineering
Volume 3, Issue 4, August 2015, Pages: 93-96
Received: Mar. 15, 2015;
Accepted: Apr. 27, 2015;
Published: Aug. 13, 2015
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M. Dashtbayazi, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
M. Sabaghi, Laser and Optics Research School, Nuclear Science and Technology Research Institute (NSTRI), Tehran, Iran
S. Marjani, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply
Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz, Journal of Electrical and Electronic Engineering.
Vol. 3, No. 4,
2015, pp. 93-96.
H. Traf, G. Holmbert and S. Eriksson “Application of switched current technique to algorithmic DA- and AD-converters”, IEEE Intl. Symp. Circuits and Systems ISCAS, pp.1549-1552, June 1991.
D.G. Nairn and C.A.T. Salama, “Current-mode algorithmic analog-to-digital converters”, IEEE Journal of Solid-State Circuits, vol. 25, pp.997 – 1004, Aug. 2002.
M. Kijima, K. Ito, K. Kamei and S. Tsukamoto, “A 6b 3GS/s Flash ADC with Background Calibration”, IEEE Custom Integrated Circuits Conference Digest of Technical Papers, pp.283–286, Sept. 2009.
Y. Nakajima, A. Sakaguchi, T. Ohkido, T. Matsumoto and M. Yotsuyanagi, “A Self-Background Calibrated 6b 2.7GS/s ADC with Cascade-Calibrated Folding-Interpolating Architecture”, IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp.266–267, June 2009.
V. Peluso, P. Vancorenland, A.M. Marques, M.S.J. Steyaert and W. Sansen, “A 900-mV Low-Power ΣΔ A/D Converter with 77-dB Dynamic Range”, IEEE Journal of Solid-State Circuits, vol. 33, pp. 1887 – 1897, Aug. 2002.
H. Roh, Y. Choi and J. Roh, “A 89-dB DR 457-W 20-kHz Bandwidth Delta-Sigma Modulator with Gain-Boosting OTAs” Analog Integrated Circuits and Signals Processing, vol. 64, pp. 173 – 182, 2010.
G.M. Yin, F. Op’t Eynde and W. Sansen, “A High-speed CMOS Comparator with 8-b Resolution”, IEEE Journal of Solid-State Circuits, vol. 27, pp. 208 – 211, Aug. 2002.
L. Yu, J.Y. Zhang, L. Wang and J.G. Lu, “A 12-bit Fully Differential SAR ADC with Dynamic Latch Comparator for Portable Physiological Monitoring Applications”, 4th international Conference on Biomedical Engineering and Informatics, vol. 1, pp. 576 – 579, Oct. 2011.
K. Balasubramanian, “A flash ADC with reduced complexity”, IEEE Transactions on Industrial Electronics, vol. 42, pp. 106 – 108, Aug. 2002.
C.H. Chan, et al, “A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator”, International SoC Des. Conf, pp. 392-395, Nov. 2009.
Y. Xu, et al, “Offset-Corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis”, IEEE New Circuits Syst. Conf, pp. 277-280, June 2011.
B.W. Chen, et al, “A 3-GHz, 22-ps/dec Dynamic Comparator using Negative Resistance Combined with Input Pair”, IEEE Asia-Pacific Conf. Circuits Syst., pp. 648-51, Dec. 2010.
C.C. Liu, et al, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure”, IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, March 2010.
B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, “Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier”, IEEE J. Solid-State Circuits, vol. 39, pp. 1148–1158, June 2004.
D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl and B. Nauta, “A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time”, IEEE ISSCC Digest of Technical Papers, pp. 314-315, Feb. 2007.
B. Goll and H. Zimmermann, “A 65nm CMOS Comparator with Modified Latch to Achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V”, IEEE ISSCC Digest of Technical Papers, pp.328–329, Feb. 2009.