Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz
Journal of Electrical and Electronic Engineering
Volume 3, Issue 4, August 2015, Pages: 93-96
Received: Mar. 15, 2015; Accepted: Apr. 27, 2015; Published: Aug. 13, 2015
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Authors
M. Dashtbayazi, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
M. Sabaghi, Laser and Optics Research School, Nuclear Science and Technology Research Institute (NSTRI), Tehran, Iran
S. Marjani, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
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Abstract
A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply
Keywords
Comparator, Negative Resistance, Optical Communication Systems, Transconductance Boosting, Dual-Rail Differential Input
To cite this article
M. Dashtbayazi, M. Sabaghi, S. Marjani, Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz, Journal of Electrical and Electronic Engineering. Vol. 3, No. 4, 2015, pp. 93-96. doi: 10.11648/j.jeee.20150304.15
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