Page Replacement Algorithm for NAND Flash Used in Mobile Devices
Journal of Electrical and Electronic Engineering
Volume 4, Issue 3, June 2016, Pages: 73-77
Received: Jun. 16, 2016; Published: Jun. 17, 2016
Views 3088      Downloads 125
Authors
Hai Jun Zhang, School of Computer Science & Information Engineering, Shanghai Institute of Technology, Shanghai, China
Wan Jun Yu, School of Computer Science & Information Engineering, Shanghai Institute of Technology, Shanghai, China
Article Tools
Follow on us
Abstract
In modern society, intelligent devices equipped with flash memory are very popular. It has many wonderful characteristics, such as small, fast, little consumption, shock resistance and so on. Flash memory is divided into NOR memory and NAND memory. The NOR memory can be quickly read with byte data which is developed into data memory for code storage. A new algorithm is needed to optimize the performance of the flash memory. In this paper, we propose a new strategy for replacement to focus on reducing the execution time of the replacement cost and I / O, which is to improve the performance of the algorithm performance. Trace-driven method has a better performance than the existing algorithms in terms of cost and execution time.
Keywords
Page Replacement Algorithms, NAND Flash Memory, Embedded Systems
To cite this article
Hai Jun Zhang, Wan Jun Yu, Page Replacement Algorithm for NAND Flash Used in Mobile Devices, Journal of Electrical and Electronic Engineering. Vol. 4, No. 3, 2016, pp. 73-77. doi: 10.11648/j.jeee.20160403.16
References
[1]
Pack, C, Kang, J, U, Park, S. Y, Kim, J. S, "Energy-aware demand paging on NAND flash-based embedded storages, "In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design.2004.
[2]
Chul. Lee, Sung Hoon Baek, Kyu Ho Park, "A Hybrid Flash File System Based on NOR and NAND Flash Memories for Embedded Devices," IEEE Translation on Computers, vol. 57, Issue. 7, July. 2008, pp. 102-1008.
[3]
Baichuan Shen. "APRA: Adaptive Page Replacement Algorithm for NAND Flash Memory Storages", 2009 International Forum on Computer Science-Technology and Applications, 12/2009.
[4]
T. Hoshi, K. Ootsu, T. Ohkawa and T. Yokota, "Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind," 2013 First International Symposium on Computing and Networking, Matsuyama, 2013, pp. 572-576.doi: 10.1109/CANDAR. 2013.102.
[5]
W. Kim and D. Shin, "Non-preemptive demand paging technique for NAND flash-based real-time embedded systems," in IEEE Transactions on Consumer Electronics, vol. 56, no. 3, pp. 1516-1523, Aug. 2010.
[6]
Megiddo, N, Modha, D," ARC:A Self-Tuning, Low Overhead Replacement Cache, "In the Proceedings of the 2nd USENIX Conference on File and Storage Technologies. 2003.
[7]
Jiang, S, Zhang, X, "LIRS: an efficient low inter-reference recency set replacement policy to improve buffer cache performance," ACM SIGMENTRICS Performance Evaluation Review archive. 2002.
[8]
S. T. On, J. Xu, B. Choi, H. Hu and B. He, "Flag Commit: Supporting Efficient Transaction Recovery in Flash-Based DBMSs," in IEEE Transactions on Knowledge and Data Engineering, vol. 24, no. 9, pp. 1624-1639, Sept. 2012.
[9]
S. A. Hussain and A. Mansoor, "FLASH modelling for wear leveling algorithms," 8th International Conference on High-capacity Optical Networks and Emerging Technologies, Riyadh, 2011, pp. 267-272.
[10]
J. Liu, S. Chen, G. Wang and T. Wu, "Page replacement algorithm based on counting bloom filter for NAND flash memory," in IEEE Transactions on Consumer Electronics, vol. 60, no. 4, pp. 636-643, Nov. 2014.
[11]
M. Lin, S. Chen and Z. Zhou, "An efficient page replacement algorithm for NAND flash memory," in IEEE Transactions on Consumer Electronics, vol. 59, no. 4, pp. 779-785, November 2013.
ADDRESS
Science Publishing Group
1 Rockefeller Plaza,
10th and 11th Floors,
New York, NY 10020
U.S.A.
Tel: (001)347-983-5186