A Fault Tolerant Voter Circuit for Triple Modular Redundant System
Journal of Electrical and Electronic Engineering
Volume 5, Issue 5, October 2017, Pages: 156-166
Received: Jun. 18, 2017; Accepted: Jun. 28, 2017; Published: Sep. 5, 2017
Views 2192      Downloads 153
Authors
Mohammed Hadifur Rahman, Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh
Shahida Rafique, Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh
Mohammad Shafiul Alam, Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh
Article Tools
Follow on us
Abstract
Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly.
Keywords
Fault Tolerance, Triple Modular Redundancy, Voter Circuit, XOR Gate, Multiplexer
To cite this article
Mohammed Hadifur Rahman, Shahida Rafique, Mohammad Shafiul Alam, A Fault Tolerant Voter Circuit for Triple Modular Redundant System, Journal of Electrical and Electronic Engineering. Vol. 5, No. 5, 2017, pp. 156-166. doi: 10.11648/j.jeee.20170505.11
Copyright
Copyright © 2017 Authors retain the copyright of this article.
This article is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
References
[1]
O. Ruano, J. A. Maestro, P. Reviriego, “A Methodology for Automatic Insertion of Selective TMR in Digital Circuits Affected by SEUs,” IEEE Transactions on Nanotechnology, vol.56, Issue 4, pp. 441-451, Aug. 2009.
[2]
J. Vial, A. Bosio, P. Girard, “Using TMR Architectures for Yield Improvement,” in IEEE International Symposium on Defect and Fault Toleranceof VLSI Systems, DFTVS, pp.7-15, Oct. 2008.
[3]
D. M. Blough, G. F. Sullivan, “A comparison of voting strategies for faulttolerant distributed systems,” in IEEE symposium on Reliable Distributed Systems, pp. 136-145, Oct. 1990.
[4]
A. Namazi, S. Askari and M. Nourani, “Highly reliable A/D converter using analog voting,” in IEEE International Conference on ComputerDesign, pp. 334-339, Oct. 2008.
[5]
R. V. Kshirsagar, R. M. Patrikar, “Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits,” in Microelectronics Reliability, vol.49, pp.1573-1577, Dec. 2009.
[6]
Tian Ban and Lirida A. B. Naviner, “A Simple Fault-tolerant Digital Voter Circuit in TMR Nanoarchitectures”, IEEE International NEWCAS Conference, Montreal, Canada 2010-06
[7]
F. L. Kastensmidt, L. Sterpone, L. Carro, and M. S. Reorda. On the Optimal Design of TripleModular Redundancy Logic for SRAM-based FPGAs. Proceedings of Design, Automation and Test in Europe, pages 1290–1295, 2005.
[8]
N. Rollins,M. Wirthlin, P. Graham, and M. Caffrey. Evaluating TMR Techniques in the Presence of Single Event Upsets. Proceedings of 6th Annual International Conference onMilitary and Aerospace Programmable Logic Devices (MAPLD), May 2003.
[9]
R. Hentschke, F. Marques, F. Lima, L. Carro, A. Susin, and R. Ries. Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy. Proceedings of the 15th Symposium on Integrated Circuits and Systems Design, page 95, September 2002.
[10]
Chen He, Margarida F. Jacome, and Gustavo de Veciana, “A Reconfiguration-Based Defect Tolerant Design Paradigm for Nanotechnologies,” IEEE Design & Test of Computers, July–August 2005, pp. 316–326.
[11]
S. Spagocci and T. Fountain, “Fault Rates in Nanochip Devices,” Proc. Electrochemical Society, 1999, vol. 98–19, pp. 582–593.
[12]
Darshan D. Thaker, Francois Impens, Isaac L. Chuang, Rajeevan Amirtharajah, and Frederic T. Chong, “Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era,” IEEE Design & Test of Computers, July–August 2005, pp. 298–305.
[13]
R. Iris Bahar, “Trends and future directions in nano structure based computing and fabrication,” International Conference on Computer Design (ICCD 06), pp. 522–528, 2006.
[14]
Huang, C, “Robust Computing with Nano-Scale Devices, Progress and challenges,” Springer, 2010.
[15]
J. Vial, A. Bosio, P. Girard, “Using TMR Architectures for Yield Improvement,” in IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, DFTVS, pp.7-15, Oct. 2008.
[16]
Snider, Gregory S., and R. Stanley Williams. "Nano/CMOS architectures using a field-programmable nanowire interconnect." Nanotechnology 18.3 (2007): 035204.
[17]
Kule, Malay, Hafizur Rahaman, and Bhargab B. Bhattacharya. "Reliable logic design with defective nano-crossbar architecture." Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), IEEE. IEEE, 2016.
[18]
Altun, Mustafa, Valentina Ciriani, and Mehdi Tahoori. "Computing with nano-crossbar arrays: Logic synthesis and fault tolerance." 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017.
[19]
Altun, Mustafa, Valentina Ciriani, and Mehdi Tahoori. "Computing with nano-crossbar arrays: Logic synthesis and fault tolerance." 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017.
[20]
Kanvitha, P., and N. Naga Raju. "FAULT SECURE ENCODER AND DECODER FOR NANO-MEMORY APPLICATIONS." (2016).
ADDRESS
Science Publishing Group
1 Rockefeller Plaza,
10th and 11th Floors,
New York, NY 10020
U.S.A.
Tel: (001)347-983-5186