CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture
Journal of Electrical and Electronic Engineering
Volume 5, Issue 6, December 2017, Pages: 242-249
Received: Jun. 15, 2017;
Accepted: Jun. 30, 2017;
Published: Jan. 2, 2018
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Mohammed Hadifur Rahman, Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh
Shahida Rafique, Institute of Science and Technology, Affiliated to National University of Bangladesh, Dhaka, Bangladesh
Mohammad Shafiul Alam, Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh
Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.
Mohammed Hadifur Rahman,
Mohammad Shafiul Alam,
CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture, Journal of Electrical and Electronic Engineering.
Vol. 5, No. 6,
2017, pp. 242-249.
D. B. Strukov and K. K. Likharev. CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology, 16: 888–900, 2005.
Y. Huang, “Logic gates and computation from assembled nanowire building blocks,” Science, 294: 1313–1317, 2001.
Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li, D. R. Stewart, J. O. Jeppesen, K. A. Nielsen, J. Fraser Stoddart, and R. S. Williams, “Nanoscale molecular-switch crossbar circuits,” Nanotechnology, 14: 462–468, Apr. 2003.
D. Whang et al., “Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems,” Nanoletters, vol. 3, no. 9, Sep. 2003, pp. 1255–1259.
H. Naeimi and A. De Hon, “A greedy algorithm for tolerating defective crosspoints in Nano PLA design,” in Proc. Int. Conf. Field-Programmable Technol., 2004, pp. 49–56.
P. Samudrala, J. Ramos, and S. Katkoori, “Selective Triple Modular Redundancy (STMR) Based Single-Event Upset (SEU) Tolerant Synthesis for FPGAs,” IEEE Transactions on Nuclear Science, Vol. 51, No. 5, pp. 2957–2969, Oct. 2004.
F. L. Kastensmidt, L. Sterpone, L. Carro, and M. S. Reorda, “On the optimal design of triple modular redundancy logic for SRAM-based FPGAs,” Design, Automation and Test in Europe, pp. 1290–1295, Vol. 2, 2005.
T. Hogg and G. S. Snider, “Defect-Tolerant Adder Circuits With Nanoscale Crossbars,” IEEE Trans. on Nanotechnology, vol. 5, no. 2, pp. 97–100, March 2006.
K. L. Jensen, “Field emitter arrays for plasma and microwave source applications,” Phys. Plasmas, vol. 6, no. 5, pp. 2241-2253, 1999.
K. K. Likharev and D. B. Strukov, “CMOL: Devices, circuits, and architectures,” in Introducing Molecular Electronics, G. Cuniberti, G. Fagas, and K. Richter, Eds. Berlin: Springer, 2005, published as Chapter 16.
Strukov D B and Likharev K K 2005 CMOL FPGA: “A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices,” in Nanotechnology 16 888–900.
Steinh¨ogl W, Schindler G, Steinlesberger G and Engelhardt M 2002 “Size effects in the electrical resistivity of polycrystalline nanowires”, Phys. Rev. B 66 075414.
Gregory S Snider, R Stanley Williams 2007, “Nano/CMOS architectures using a field-programmable nanowire interconnect”, Nanotechnology 1835204.
International Technology Roadmap for Semiconductors (ITRS) 2005 Available online at http://public.itrs.net/
Veldhorst, M., et al. "Silicon CMOS architecture for a spin-based quantum computer." Ar Xiv preprint ar Xiv: 1609.09700 (2016).
Prinzie, Jeffrey, et al. "A single-event upset robust, 2.2 GHz to 3.2GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS." Solid-State Circuits Conference (A-SSCC), 2016 IEEE Asian. IEEE, 2016.
Kanvitha, P., and N. Naga Raju. "FAULT SECURE ENCODER ANDDECODER FOR NANO-MEMORY APPLICATIONS." (2016).
Altun, Mustafa, Valentina Ciriani, and Mehdi Tahoori. "Computing with nano-crossbar arrays: Logic synthesis and fault tolerance." 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017.