Journal of Electrical and Electronic Engineering
Volume 7, Issue 4, August 2019, Pages: 95-100
Received: Aug. 18, 2019;
Accepted: Sep. 23, 2019;
Published: Oct. 9, 2019
Views 17 Downloads 9
Andrey Molyakov, Institute of Information Technologies and Cybersecurity, Russian State University for the Humanities, Moscow, Russia
Author describes military and special supercomputer centers and networks by example CT-2. Work on highly productive and promising SC with a globally addressable memory and multi-thread architecture is carried out within the framework of the CT-2 project. The eponymous supercomputer belongs to the class of strategic supercomputers. The code name used is CT-2 (full name Qin Tao -2) - this is the idiom in the Chinese name “The main project in the interests of special studies of military intelligence of the Ministry of Defense of China”. Due to using of massive multi-thread streaming architecture increased tolerance to delays in performing operations with memory and the network, effectively support working with program models in the form of static graphs of data flows. Because of this, it will successfully cope with the processing in real time of multiple data streams and work effectively through a single address space with a huge memory capacity of several tens of petabytes, even in the mode of intensive irregular work with it, it will have exceptional fault tolerance and availability. The amount of available memory for the user program is 32PB, the physical memory is 64PB, which is done for hot standby. According to information received in 2011, the initially massive multi-thread microprocessor CT-2 with asynchronous threads for information systems has also become hybrid, it has enhanced numerical processing power - SIMD operations on short vectors have been introduced, as well as elements of modern graphic processors in the form of synchronous threads.
China Net: Military and Special Supercomputer Centers, Journal of Electrical and Electronic Engineering. Special Issue: Science Innovation.
Vol. 7, No. 4,
2019, pp. 95-100.
N. Sun, D. Kahaner, D. Chen. High-performance Computing in China: Research and Applications. International Journal of High Performance Computing Applications, 24 (4), 21. 09. 2010, pp. 363-409.
X. Guo, D. Lecarpentier, P. Oster, M. Parsons, L. Smith. Investigation Report on Existing HPC Initiatives. European Exascale Software Initiative, CSA-2010-261513, 29. 09. 2010, 44 pp.
P. Kogge et al. ExaScale Computing Study: Technology Challenges in Achiving Exascale Systems. DARPA IPTO, US Air Force Research Laboratory, September 28, 2008, 278 pp.
Molyakov, А. S. New Multilevel Architecture of Secured Supercomputers/A. S. Molyakov//Current Trends in Computer Sciences & Applications 1 (3) – 2019. – PP. 57-59. – ISSN: 2643-6744 – https://lupinepublishers.com/computer-science-journal/special-issue/CTCSA.MS.ID.000112.pdf. – DOI: 10.32474/CTCSA.2019.01.000112.
Molyakov, A. S. Technological Methods Analysis in the Field of Exaflops Supercomputers Development Approaching/A. S. Molyakov, L. K. Eisymont//Global Journal of Computer Science and Technology: Information & Technology. – 2017. – № 1 (17). – РР. 37-44.
Molyakov, A. S. A Prototype Computer with Non-von Neumann Architecture Based on Strategic Domestic J7 Microprocessor/A. S. Molyakov//Automatic Control and Computer Sciences. – 2016. – № 50 (8). – РР. 682-686.
Rao A. et al. Effect of Grammar on Security of Long Passwords. CODASPY’13, February 18-20, 2013, 8 pp.
Archana A., Kohila N. Probabilistic Context-Free Grammar (PCFG) Wiser Password Cracking Techniques. International Journal of Research in Computer Applications and Robotics, February 2016, vol. 4, Issue 2, p. 1-6.
Goldstein Seth Copen, Schmit Herman, Budiu Mihai, Cadambi Srihari, Moe Matt, Taylor R. Reed. PipeRench: a reconfigurable architecture and compiler. Computer, April 2000, pp. 70-77.
Vahey М., et al. “MONARCH: A First Generation Polymorphic Computing Processor”, Raytheon, 2007, 2 pp.
Xu Guo, Meeta Srivastav, Sian Huang, Denesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont. Silicon Implementation of SHA-3 Finalists: BLAKE, Grostl, JH, Keссak and Skein. 2011, 16 pp.
Meeta Srivastav, Xu Guo, Sian Huang, Denesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont. Design and Benchmarking of an ASIC with Five SHA-3 Finalist Candidates. Center for Embedded Systems for Critical Applications (CESCA), USA, April 20, 2012, 27 pp.
Xu Guo, Meeta Srivastav, Sian Huang, Denesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont. ASIC Implementations of Five SHA-3 Finalists. 2012, 6 pp.
Patrice Guillet, Enrico Pargaetzi, Martin Zoller. Silicon Implementation of Second-Round SHA-3 Candidates. February 2010, Swiss Federal Institute of Technology Zurich, Integrated System Laboratory, 2010, 46 pp.
Frank K. Gurkaynak, Kris Gaj, Beat Muheim, Ekawat Homsirikamol, Christoph Keller, Marcin Rogawski, Hubert Kaeslin, Jens-Peter Kaps. Lessons Learned from Designing a 65nm ASIC for Third Round SHA-3 Candidates. ETH Zurich - George Mason University, 22-23 March 2012, 65 slides.