Electrical Fast Transients (EFT) pulses may cause a large number of circuits to fail. Switching power supplies, inductors, contact relays, and high voltage switches electrically or electromagnetically strike the data, address and control lines of processors, memory elements, or even analog parts and leads to soft or permanent errors. In general, compliant test is accomplished to address the susceptibility of circuits to EFT pulses. However, extremely high cost of these tests encounters the compliant test with difficulty. As a result, in this paper a low-cost EFT simulator circuit is proposed to locate the vulnerable parts of the circuit. The approach is easily applicable to any point of any circuit. The design is performed such that the proposed circuit does not damage the Equipment Under Test (EUT). Experimental results show that the proposed approach effectively detects the vulnerable circuits and practically has been used at the design phase of the DTPS-8C device.
| Published in |
Journal of Electrical and Electronic Engineering (Volume 3, Issue 2-1)
This article belongs to the Special Issue Research and Practices in Electrical and Electronic Engineering in Developing Countries |
| DOI | 10.11648/j.jeee.s.2015030201.26 |
| Page(s) | 72-77 |
| Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
| Copyright |
Copyright © The Author(s), 2024. Published by Science Publishing Group |
Electromagnetic Compatibility, EFT/B, Switching, Protection Devices
| [1] | IEC61000-4-4, "Electromagnetic compatibility (EMC), Part 4-4: Testing & measurement techniques – Electrical fast transient/ Burst immunity test", edition 3.0, 2012. |
| [2] | J. R. Barnes, "Designing Electronic Systems for ESD Immunity", Conformity magazine, Feb. 2003. Online at: http://www.dbicorporation.com/esd-art3.pdf. |
| [3] | S. Hyung, J. Young, "Analysis of Coupling Mechanism and Solution for EFT Noise on Semiconductor Device Level", Proceedings of the International Conference on Electromagnetic Interference and Compatibility, New Delhi, India, 6-8 Dec. 1999. |
| [4] | E. Rogers, "Understanding Boost Power Stages in Switch mode Power Supplies", Application Report, Mixed Signal Products, TI Literature Number SLVA061, 1999. Online at: http://www.ti.com/lit/an/slva061/slva061.pdf. |
| [5] | A. Tamuri, "Nanoseconds Switching for High Voltage Circuit Using Avalanche Transistors", Applied physics research, Vol. 1, No. 2, 2009. Online at: http://www.ccsenet.org/journal/index.php/apr/article/viewFile/3287/3601. |
| [6] | B. Gh. Family, V. H. Vaghef, and M. Shabro, "A Method for Determining the Critical Parts of Electronic Circuits into EFT/B", 7thSASTech international conference, Bandar-Abbas, Iran, 2013. |
APA Style
Behnam Gholamrezazadeh Family, Vahid Hamiyaty Vaghef, Maryam Shabro. (2015). Cost Effective Method to Locate the Vulnerable Nodes of Circuits Against the Electrical Fast Transients. Journal of Electrical and Electronic Engineering, 3(2-1), 72-77. https://doi.org/10.11648/j.jeee.s.2015030201.26
ACS Style
Behnam Gholamrezazadeh Family; Vahid Hamiyaty Vaghef; Maryam Shabro. Cost Effective Method to Locate the Vulnerable Nodes of Circuits Against the Electrical Fast Transients. J. Electr. Electron. Eng. 2015, 3(2-1), 72-77. doi: 10.11648/j.jeee.s.2015030201.26
AMA Style
Behnam Gholamrezazadeh Family, Vahid Hamiyaty Vaghef, Maryam Shabro. Cost Effective Method to Locate the Vulnerable Nodes of Circuits Against the Electrical Fast Transients. J Electr Electron Eng. 2015;3(2-1):72-77. doi: 10.11648/j.jeee.s.2015030201.26
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Download@article{10.11648/j.jeee.s.2015030201.26,
author = {Behnam Gholamrezazadeh Family and Vahid Hamiyaty Vaghef and Maryam Shabro},
title = {Cost Effective Method to Locate the Vulnerable Nodes of Circuits Against the Electrical Fast Transients},
journal = {Journal of Electrical and Electronic Engineering},
volume = {3},
number = {2-1},
pages = {72-77},
doi = {10.11648/j.jeee.s.2015030201.26},
url = {https://doi.org/10.11648/j.jeee.s.2015030201.26},
eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.s.2015030201.26},
abstract = {Electrical Fast Transients (EFT) pulses may cause a large number of circuits to fail. Switching power supplies, inductors, contact relays, and high voltage switches electrically or electromagnetically strike the data, address and control lines of processors, memory elements, or even analog parts and leads to soft or permanent errors. In general, compliant test is accomplished to address the susceptibility of circuits to EFT pulses. However, extremely high cost of these tests encounters the compliant test with difficulty. As a result, in this paper a low-cost EFT simulator circuit is proposed to locate the vulnerable parts of the circuit. The approach is easily applicable to any point of any circuit. The design is performed such that the proposed circuit does not damage the Equipment Under Test (EUT). Experimental results show that the proposed approach effectively detects the vulnerable circuits and practically has been used at the design phase of the DTPS-8C device.},
year = {2015}
}
TY - JOUR T1 - Cost Effective Method to Locate the Vulnerable Nodes of Circuits Against the Electrical Fast Transients AU - Behnam Gholamrezazadeh Family AU - Vahid Hamiyaty Vaghef AU - Maryam Shabro Y1 - 2015/02/10 PY - 2015 N1 - https://doi.org/10.11648/j.jeee.s.2015030201.26 DO - 10.11648/j.jeee.s.2015030201.26 T2 - Journal of Electrical and Electronic Engineering JF - Journal of Electrical and Electronic Engineering JO - Journal of Electrical and Electronic Engineering SP - 72 EP - 77 PB - Science Publishing Group SN - 2329-1605 UR - https://doi.org/10.11648/j.jeee.s.2015030201.26 AB - Electrical Fast Transients (EFT) pulses may cause a large number of circuits to fail. Switching power supplies, inductors, contact relays, and high voltage switches electrically or electromagnetically strike the data, address and control lines of processors, memory elements, or even analog parts and leads to soft or permanent errors. In general, compliant test is accomplished to address the susceptibility of circuits to EFT pulses. However, extremely high cost of these tests encounters the compliant test with difficulty. As a result, in this paper a low-cost EFT simulator circuit is proposed to locate the vulnerable parts of the circuit. The approach is easily applicable to any point of any circuit. The design is performed such that the proposed circuit does not damage the Equipment Under Test (EUT). Experimental results show that the proposed approach effectively detects the vulnerable circuits and practically has been used at the design phase of the DTPS-8C device. VL - 3 IS - 2-1 ER -
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