Journal of Electrical and Electronic Engineering

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CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture

Received: 15 June 2017    Accepted: 30 June 2017    Published: 02 January 2018
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Abstract

Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.

DOI 10.11648/j.jeee.20170506.15
Published in Journal of Electrical and Electronic Engineering (Volume 5, Issue 6, December 2017)
Page(s) 242-249
Creative Commons

This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.

Copyright

Copyright © The Author(s), 2024. Published by Science Publishing Group

Keywords

Quaded Structure, Reliability, Cmol, Nand Gate, Nano Architecture

References
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[4] D. Whang et al., “Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems,” Nanoletters, vol. 3, no. 9, Sep. 2003, pp. 1255–1259.
[5] H. Naeimi and A. De Hon, “A greedy algorithm for tolerating defective crosspoints in Nano PLA design,” in Proc. Int. Conf. Field-Programmable Technol., 2004, pp. 49–56.
[6] P. Samudrala, J. Ramos, and S. Katkoori, “Selective Triple Modular Redundancy (STMR) Based Single-Event Upset (SEU) Tolerant Synthesis for FPGAs,” IEEE Transactions on Nuclear Science, Vol. 51, No. 5, pp. 2957–2969, Oct. 2004.
[7] F. L. Kastensmidt, L. Sterpone, L. Carro, and M. S. Reorda, “On the optimal design of triple modular redundancy logic for SRAM-based FPGAs,” Design, Automation and Test in Europe, pp. 1290–1295, Vol. 2, 2005.
[8] T. Hogg and G. S. Snider, “Defect-Tolerant Adder Circuits With Nanoscale Crossbars,” IEEE Trans. on Nanotechnology, vol. 5, no. 2, pp. 97–100, March 2006.
[9] K. L. Jensen, “Field emitter arrays for plasma and microwave source applications,” Phys. Plasmas, vol. 6, no. 5, pp. 2241-2253, 1999.
[10] K. K. Likharev and D. B. Strukov, “CMOL: Devices, circuits, and architectures,” in Introducing Molecular Electronics, G. Cuniberti, G. Fagas, and K. Richter, Eds. Berlin: Springer, 2005, published as Chapter 16.
[11] Strukov D B and Likharev K K 2005 CMOL FPGA: “A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices,” in Nanotechnology 16 888–900.
[12] Steinh¨ogl W, Schindler G, Steinlesberger G and Engelhardt M 2002 “Size effects in the electrical resistivity of polycrystalline nanowires”, Phys. Rev. B 66 075414.
[13] Gregory S Snider, R Stanley Williams 2007, “Nano/CMOS architectures using a field-programmable nanowire interconnect”, Nanotechnology 1835204.
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[16] Prinzie, Jeffrey, et al. "A single-event upset robust, 2.2 GHz to 3.2GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS." Solid-State Circuits Conference (A-SSCC), 2016 IEEE Asian. IEEE, 2016.
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Author Information
  • Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh

  • Institute of Science and Technology, Affiliated to National University of Bangladesh, Dhaka, Bangladesh

  • Department of Electrical and Electronic Engineering, University of Dhaka, Dhaka, Bangladesh

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  • APA Style

    Mohammed Hadifur Rahman, Shahida Rafique, Mohammad Shafiul Alam. (2018). CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture. Journal of Electrical and Electronic Engineering, 5(6), 242-249. https://doi.org/10.11648/j.jeee.20170506.15

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    ACS Style

    Mohammed Hadifur Rahman; Shahida Rafique; Mohammad Shafiul Alam. CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture. J. Electr. Electron. Eng. 2018, 5(6), 242-249. doi: 10.11648/j.jeee.20170506.15

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    AMA Style

    Mohammed Hadifur Rahman, Shahida Rafique, Mohammad Shafiul Alam. CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture. J Electr Electron Eng. 2018;5(6):242-249. doi: 10.11648/j.jeee.20170506.15

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  • @article{10.11648/j.jeee.20170506.15,
      author = {Mohammed Hadifur Rahman and Shahida Rafique and Mohammad Shafiul Alam},
      title = {CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture},
      journal = {Journal of Electrical and Electronic Engineering},
      volume = {5},
      number = {6},
      pages = {242-249},
      doi = {10.11648/j.jeee.20170506.15},
      url = {https://doi.org/10.11648/j.jeee.20170506.15},
      eprint = {https://download.sciencepg.com/pdf/10.11648.j.jeee.20170506.15},
      abstract = {Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.},
     year = {2018}
    }
    

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    T1  - CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture
    AU  - Mohammed Hadifur Rahman
    AU  - Shahida Rafique
    AU  - Mohammad Shafiul Alam
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    JF  - Journal of Electrical and Electronic Engineering
    JO  - Journal of Electrical and Electronic Engineering
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    EP  - 249
    PB  - Science Publishing Group
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    AB  - Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.
    VL  - 5
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    ER  - 

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