Development and Prospect of Lithography Technology on Chips

Sun Bing; Liu Li; Zhang Yan; Tian Feng; Qi Jingai

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Development and Prospect of Lithography Technology on Chips

Sun Bing, Liu Li, Zhang Yan, Tian Feng, Qi Jingai

Published in Asia-Pacific Journal of Electronic and Electrical Engineering (Volume 1, Issue 2)

Received: 17 September 2019 Accepted: 16 October 2019 Published: 29 October 2019

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Abstract

rom Internet PCs at the beginning of this century to smart mobile devices in the 2010s, all these new applications rely on the rapid improvement of processor chips. Increasing the integration degree can reduce the cost of a single transistor. In the planar CMOS process, reducing the feature size can increase the speed of the transistor switch, and also enhance the itintegry of the transistor, opening up new market applications for the chip.When the current I passing through the lead line, the design formula for voltage that should be added at both ends of the lead line with different lengths, widths, and heights should be followed by the principle of 1~3mV/μm with the wire length. At the same time, ΔU should be coordinated with resistance value R of the lead line. The lead resistance can be selected according to the table in the text. Photolithography is a kind of precision micromachining technology, so that the graphics on the mask plate are copied to the photoresist film; Finally, using etching technology, the graphics are transferred to the silicon substrate. To this end, the common wavelength of photolithography and precision mechanical process of photolithography are discussed. It is expected that the latest process of 3nm will begin by 2020. The use of far-ultraviolet wavelengths, coupled with large digital aperture lenses, can achieve a feature size of 1.5 nm, which is expected to support Moore's law development until 2030.

Published in	Asia-Pacific Journal of Electronic and Electrical Engineering (Volume 1, Issue 2)
Page(s)	15-20
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2024. Published by Science Publishing Group

Keywords

Transistor, Integriticd Circuit, Feature Siz, Wire Resistance, Photolithography, Mask Plate, Moore's Law

References

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[7]	郝跃，邵波涛，马晓华，等.UI SI中铜互连及其可靠性的研究与进展[J].西安电子科技大学学报(自然科学版)，2005, 32 (4) 627-633.
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[16]	A. R. Mirszal, Artificial Intelligence (M), Great Britain, London, Chapman and Hall, 1990, 97-105.

Cite This Article

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APA Style

Sun Bing, Liu Li, Zhang Yan, Tian Feng, Qi Jingai. (2019). Development and Prospect of Lithography Technology on Chips. Asia-Pacific Journal of Electronic and Electrical Engineering, 1(2), 15-20.

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ACS Style

Sun Bing; Liu Li; Zhang Yan; Tian Feng; Qi Jingai. Development and Prospect of Lithography Technology on Chips. Asia-Pac. J. Electron. Electr. Eng. 2019, 1(2), 15-20.

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AMA Style

Sun Bing, Liu Li, Zhang Yan, Tian Feng, Qi Jingai. Development and Prospect of Lithography Technology on Chips. Asia-Pac J Electron Electr Eng. 2019;1(2):15-20.

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@article{10043217,
  author = {Sun Bing and Liu Li and Zhang Yan and Tian Feng and Qi Jingai},
  title = {Development and Prospect of Lithography Technology on Chips},
  journal = {Asia-Pacific Journal of Electronic and Electrical Engineering},
  volume = {1},
  number = {2},
  pages = {15-20},
  url = {https://www.sciencepublishinggroup.com/article/10043217},
  abstract = {rom Internet PCs at the beginning of this century to smart mobile devices in the 2010s, all these new applications rely on the rapid improvement of processor chips. Increasing the integration degree can reduce the cost of a single transistor. In the planar CMOS process, reducing the feature size can increase the speed of the transistor switch, and also enhance the itintegry of the transistor, opening up new market applications for the chip.When the current I passing through the lead line, the design formula for voltage that should be added at both ends of the lead line with different lengths, widths, and heights should be followed by the principle of 1~3mV/μm with the wire length. At the same time, ΔU should be coordinated with resistance value R of the lead line. The lead resistance can be selected according to the table in the text. Photolithography is a kind of precision micromachining technology, so that the graphics on the mask plate are copied to the photoresist film; Finally, using etching technology, the graphics are transferred to the silicon substrate. To this end, the common wavelength of photolithography and precision mechanical process of photolithography are discussed. It is expected that the latest process of 3nm will begin by 2020. The use of far-ultraviolet wavelengths, coupled with large digital aperture lenses, can achieve a feature size of 1.5 nm, which is expected to support Moore's law development until 2030.},
 year = {2019}
}

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TY  - JOUR
T1  - Development and Prospect of Lithography Technology on Chips
AU  - Sun Bing
AU  - Liu Li
AU  - Zhang Yan
AU  - Tian Feng
AU  - Qi Jingai
Y1  - 2019/10/29
PY  - 2019
T2  - Asia-Pacific Journal of Electronic and Electrical Engineering
JF  - Asia-Pacific Journal of Electronic and Electrical Engineering
JO  - Asia-Pacific Journal of Electronic and Electrical Engineering
SP  - 15
EP  - 20
PB  - Science Publishing Group
UR  - http://www.sciencepg.com/article/10043217
AB  - rom Internet PCs at the beginning of this century to smart mobile devices in the 2010s, all these new applications rely on the rapid improvement of processor chips. Increasing the integration degree can reduce the cost of a single transistor. In the planar CMOS process, reducing the feature size can increase the speed of the transistor switch, and also enhance the itintegry of the transistor, opening up new market applications for the chip.When the current I passing through the lead line, the design formula for voltage that should be added at both ends of the lead line with different lengths, widths, and heights should be followed by the principle of 1~3mV/μm with the wire length. At the same time, ΔU should be coordinated with resistance value R of the lead line. The lead resistance can be selected according to the table in the text. Photolithography is a kind of precision micromachining technology, so that the graphics on the mask plate are copied to the photoresist film; Finally, using etching technology, the graphics are transferred to the silicon substrate. To this end, the common wavelength of photolithography and precision mechanical process of photolithography are discussed. It is expected that the latest process of 3nm will begin by 2020. The use of far-ultraviolet wavelengths, coupled with large digital aperture lenses, can achieve a feature size of 1.5 nm, which is expected to support Moore's law development until 2030.
VL  - 1
IS  - 2
ER  -

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Author Information

Sun Bing

Tianjin Metrology Supervision and Testing Science Research Institute, Tianjin, China
Liu Li

University Office and Information College, Hebei University of Technology, Tianjin, China
Zhang Yan

University Office and Information College, Hebei University of Technology, Tianjin, China
Tian Feng

University Office and Information College, Hebei University of Technology, Tianjin, China
Qi Jingai

University Office and Information College, Hebei University of Technology, Tianjin, China

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Plain Text BibTeX RIS

APA Style

Sun Bing, Liu Li, Zhang Yan, Tian Feng, Qi Jingai. (2019). Development and Prospect of Lithography Technology on Chips. Asia-Pacific Journal of Electronic and Electrical Engineering, 1(2), 15-20.

Copy | Download

ACS Style

Sun Bing; Liu Li; Zhang Yan; Tian Feng; Qi Jingai. Development and Prospect of Lithography Technology on Chips. Asia-Pac. J. Electron. Electr. Eng. 2019, 1(2), 15-20.

Copy | Download

AMA Style

Sun Bing, Liu Li, Zhang Yan, Tian Feng, Qi Jingai. Development and Prospect of Lithography Technology on Chips. Asia-Pac J Electron Electr Eng. 2019;1(2):15-20.

Copy | Download

@article{10043217,
  author = {Sun Bing and Liu Li and Zhang Yan and Tian Feng and Qi Jingai},
  title = {Development and Prospect of Lithography Technology on Chips},
  journal = {Asia-Pacific Journal of Electronic and Electrical Engineering},
  volume = {1},
  number = {2},
  pages = {15-20},
  url = {https://www.sciencepublishinggroup.com/article/10043217},
  abstract = {rom Internet PCs at the beginning of this century to smart mobile devices in the 2010s, all these new applications rely on the rapid improvement of processor chips. Increasing the integration degree can reduce the cost of a single transistor. In the planar CMOS process, reducing the feature size can increase the speed of the transistor switch, and also enhance the itintegry of the transistor, opening up new market applications for the chip.When the current I passing through the lead line, the design formula for voltage that should be added at both ends of the lead line with different lengths, widths, and heights should be followed by the principle of 1~3mV/μm with the wire length. At the same time, ΔU should be coordinated with resistance value R of the lead line. The lead resistance can be selected according to the table in the text. Photolithography is a kind of precision micromachining technology, so that the graphics on the mask plate are copied to the photoresist film; Finally, using etching technology, the graphics are transferred to the silicon substrate. To this end, the common wavelength of photolithography and precision mechanical process of photolithography are discussed. It is expected that the latest process of 3nm will begin by 2020. The use of far-ultraviolet wavelengths, coupled with large digital aperture lenses, can achieve a feature size of 1.5 nm, which is expected to support Moore's law development until 2030.},
 year = {2019}
}

Copy | Download

TY  - JOUR
T1  - Development and Prospect of Lithography Technology on Chips
AU  - Sun Bing
AU  - Liu Li
AU  - Zhang Yan
AU  - Tian Feng
AU  - Qi Jingai
Y1  - 2019/10/29
PY  - 2019
T2  - Asia-Pacific Journal of Electronic and Electrical Engineering
JF  - Asia-Pacific Journal of Electronic and Electrical Engineering
JO  - Asia-Pacific Journal of Electronic and Electrical Engineering
SP  - 15
EP  - 20
PB  - Science Publishing Group
UR  - http://www.sciencepg.com/article/10043217
AB  - rom Internet PCs at the beginning of this century to smart mobile devices in the 2010s, all these new applications rely on the rapid improvement of processor chips. Increasing the integration degree can reduce the cost of a single transistor. In the planar CMOS process, reducing the feature size can increase the speed of the transistor switch, and also enhance the itintegry of the transistor, opening up new market applications for the chip.When the current I passing through the lead line, the design formula for voltage that should be added at both ends of the lead line with different lengths, widths, and heights should be followed by the principle of 1~3mV/μm with the wire length. At the same time, ΔU should be coordinated with resistance value R of the lead line. The lead resistance can be selected according to the table in the text. Photolithography is a kind of precision micromachining technology, so that the graphics on the mask plate are copied to the photoresist film; Finally, using etching technology, the graphics are transferred to the silicon substrate. To this end, the common wavelength of photolithography and precision mechanical process of photolithography are discussed. It is expected that the latest process of 3nm will begin by 2020. The use of far-ultraviolet wavelengths, coupled with large digital aperture lenses, can achieve a feature size of 1.5 nm, which is expected to support Moore's law development until 2030.
VL  - 1
IS  - 2
ER  -

Copy | Download