Abstract: rom Internet PCs at the beginning of this century to smart mobile devices in the 2010s, all these new applications rely on the rapid improvement of processor chips. Increasing the integration degree can reduce the cost of a single transistor. In the planar CMOS process, reducing the feature size can increase the speed of the transistor switch, and also enhance the itintegry of the transistor, opening up new market applications for the chip.When the current I passing through the lead line, the design formula for voltage that should be added at both ends of the lead line with different lengths, widths, and heights should be followed by the principle of 1~3mV/μm with the wire length. At the same time, ΔU should be coordinated with resistance value R of the lead line. The lead resistance can be selected according to the table in the text. Photolithography is a kind of precision micromachining technology, so that the graphics on the mask plate are copied to the photoresist film; Finally, using etching technology, the graphics are transferred to the silicon substrate. To this end, the common wavelength of photolithography and precision mechanical process of photolithography are discussed. It is expected that the latest process of 3nm will begin by 2020. The use of far-ultraviolet wavelengths, coupled with large digital aperture lenses, can achieve a feature size of 1.5 nm, which is expected to support Moore's law development until 2030.Abstract: rom Internet PCs at the beginning of this century to smart mobile devices in the 2010s, all these new applications rely on the rapid improvement of processor chips. Increasing the integration degree can reduce the cost of a single transistor. In the planar CMOS process, reducing the feature size can increase the speed of the transistor switch, and ...Show More
